1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to the compensation for device feature non-uniformities across the wafer area by adapting exposure conditions of a step and scan photolithography tool.
2. Description of the Related Art
Fabrication of integrated circuits requires the precise formation of very small features with a very small tolerance for error. Such features may be formed in a material layer formed above an appropriate substrate, such as a silicon substrate. These features of precisely controlled size are generated by patterning the material layer by performing known photo-lithography and etching processes, wherein a masking layer is formed over the material layer to be etched to define these features. Generally, a masking layer may consist of or is formed by means of a layer of photoresist that is patterned by a lithographic process. During the lithographic process, the resist may be spin-coated onto the wafer surface and is then selectively exposed to ultraviolet radiation. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Since the dimensions of the patterns in sophisticated integrated circuits are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure specifying the consistent ability to print images of a minimum size under conditions of predefined manufacturing variations. One important factor in improving the resolution is represented by the lithographic process, in which patterns contained in a photo mask or reticle are optically transferred to the layer of photo-resist via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used. The quality of the lithographic imagery is extremely important in creating very small feature sizes.
Of at least comparable importance, however, is the accuracy with which an image can be positioned on the surface of the substrate. Integrated circuits are typically fabricated by sequentially patterning material layers, wherein features on successive material layers bear a spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previously patterned material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure and development. Furthermore, non-uniformities of the etching processes can also lead to variations of the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern for the current material layer to the pattern of the previously formed material layer while photolithographically transferring the image onto the substrate.
A further aspect affecting the quality of device features and hence the electrical behavior thereof is the employment of substrates, i.e., wafers, having an increased diameter, wherein a typical wafer diameter is 200 mm with the prospect of 300 mm to become the standard wafer diameter in modern semiconductor facilities. Large diameters, although desirable in view of economical considerations, may, however, exacerbate the problem of non-uniformities across the wafer surface, especially as the minimum device dimensions, also referred to as critical dimensions (CD), steadily decrease. It is therefore desirable to minimize feature variations not only from wafer to wafer but also across the entire wafer surface to allow semiconductor manufacturers to use processes in which the tolerances may be set more tightly so as to achieve improved production yield while at the same time enhance device performance in view of, for example, operational speed. Otherwise, the fluctuations across the wafer (and the wafer-to-wafer variations) may be taken into account, thereby requiring a circuit design that tolerates higher process discrepancies.
One appropriate way to reduce wafer non-uniformities is offered by the presently applied lithography technique in which a plurality of individual dies or exposure fields are exposed in a step and scan process. That is, each exposure event includes its specific alignment procedure along with a specified tool setting. Thus, the lithography process may be used to compensate for at least some of the wafer non-uniformities generated during the processing of the wafer. To this end, conventionally one or more electrical characteristics are measured and are related to one or more lithography tool specific parameters to readjust the tool setting for each position of the exposure field on the basis of these measurement results. A conventional approach for such a tool control is based on the distribution of one or more electrical parameters across the wafer surface to derive a so-called position dependent exposure map, denoted as E(x,y) with x,y being position coordinates on the wafer, by, for example, a linear procedure. The exposure map E(x,y) may include one or more tool parameters or any other parameters required for adjusting the tool characteristics at the position x,y. A linear approach may be appropriate when it is assumed that the relationship between the exposure map and the electrical characteristics needs to be sufficiently correct within a relatively small range of the electrical characteristic only. Thus, the linear relationship may be expressed as follows:E(x,y)=γCDtarget(x,y)+b,  (1)wherein CDtarget(x,y) represents a setpoint for the critical dimension at the position x,y and γ represents a constant relating the critical dimension of a feature, for example the gate length of a transistor, to the corresponding tool characteristic, such as depth of focus, alignment specific parameters, and the like. The constant b indicates a parameter for adjusting the offset of exposure map E in the above linear relationship (1). The position dependent critical dimension CDtarget(x,y) may, in turn, be composed of a position independent term CDtarget, indicating the desired design CD for the feature under consideration, and a position dependent deviation or offset CDoffset(x,y). Thus, CDtarget(x,y) may be written as:CDtarget(x,y)=CDtarget+CDoffset(x,y)  (2)
The position dependent offset CDoffset(x,y) may be obtained by a correlation between the offset CDoffset(x,y) and measurement data of one or more electrical parameters, indicated hereinafter as Pel, wherein the electrical parameter Pel may be considered as one or more parameters that are well accessible by measurement and also reasonably assignable to the critical dimension. For instance, the rise and fall times of transistor elements may be determined by measurement after completion of the transistor elements and may be used to establish a suitable correlation between the measurement data and the offset CDoffset(x,y). The position dependent offset CDoffset(x,y) may then be expressed by:CDoffset(x,y)=α(Pel(x,y)−Peltarget)  (3)wherein Peltarget represents a design value of the electrical parameter under interest and α represents a constant describing the degree of influence of the difference of the measurement data Pel(x,y) and the target value Peltarget on the position dependent offset CDoffset(x,y).
To obtain a sufficiently “strong” correlation between the electrical parameter Pel(x,y) and the position dependent offset CDoffset(x,y), a large amount of measurement data is usually necessary that may be averaged over a large number of substrates. Although the above discussed approach allows a moderate improvement in reducing wafer specific non-uniformities, the overall effect on the process control is limited owing to the required averaging of a large number of substrates that may even be processed in different “threads” of process tools, depending on process utilization and facility internal requirements. As a consequence, the above process control strategy only addresses fluctuations concerning all of the substrates irrespective of the process “history” of individual groups of substrates, since the correlation described by equation (3) is a feedback loop only, wherein effects not common to all substrates are “blurred,” especially as the delay between the lithography process and the receipt of the measurement data Pel(x,y) is significant. Moreover, the blurring of process history specific fluctuations leads to a control effect for compensating for a “quasi-static” distribution of the wafer non-uniformities, wherein such a quasi-static distribution in many cases may be an over-simplified assumption due to the different process threads of different groups of substrates, thereby unduly restricting the control quality and thus the device characteristics.
In view of the above-identified problems, it is therefore desirable to develop a control strategy for a lithography process, wherein one or more of the above constraints may be avoided or at least reduced.